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(R)
X9401
Low Noise/Low Power/SPI Bus
Data Sheet October 12, 2006 FN8190.3
Quad, 64 Tap, Digitally Controlled Potentiometer (XDCPTM)
FEATURES * * * * * * * * * * * * * Quad-4 separate pots, 64 taps/pot Nonvolatile storage of wiper position Four Nonvolatile Data Registers for Each Pot 16-bytes of EEPROM memory SPI serial interface RTotal = 10k Wiper resistance = 150 typical Standby current < 1A (total package) Operating current < 400A max. VCC = 2.7V to 5V Package-24 Ld SOIC 100 year data retention Pb-free plus anneal available (RoHS compliant)
DESCRIPTION The X9401 integrates 4 digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated microcircuit. The digitally controlled potentiometer is implemented using 64 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the SPI bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and 4 nonvolatile Data Registers (DR0:DR3) that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array through the switches. Power-up recalls the contents of DR0 to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing.
BLOCK DIAGRAM
VCC VSS R0 R1 Pot 0 Wiper Counter Register (WCR) VH0/RH0 R0 R1 Wiper Counter Register (WCR) VH2/RH2
HOLD CS SCK SO SI A0 A1 WP Interface and Control Circuitry Data
R2 R3
VL0/RL0 VW0/RW0
R2 R3
Resistor Array Pot 2
VL2/RL2 VW2/RW2
8 VW1/RW1 R0 R1 Wiper Counter Register (WCR) Resistor Array Pot 1 VH1/RH1 R0 R1 Wiper Counter Register (WCR) VW3/RW3 VH3/RH3
R2 R3
VL1/RL1
R2 R3
Resistor Array Pot 3
VL3/RL3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
X9401 Ordering Information
PART NUMBER X9401WS24IZ (Note) X9401WS24I-2.7* X9401WS24IZ-2.7* (Note) PART MARKING X9401WS ZI X9401WS G X9401WS ZG VCC LIMITS (V) 5 10% 2.7 to 5.5 POTENTIOMETER TEMP ORGANIZATION (k) RANGE (C) 10 10 -40 to 85 -40 to 85 -40 to 85 PACKAGE 24 Ld SOIC (300 mil) (Pb-free) 24 Ld SOIC (300 mil) 24 Ld SOIC (300 mil) (Pb-free) PKG. DWG. # MDP0027 M24.3 MDP0027
*Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
PIN DESCRIPTIONS Host Interface Pins Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input SI is the serial data input pin. All opcodes, byte addresses and data to be written to the pots and pot registers are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The SCK input is used to clock data into and out of the X9401. Chip Select (CS) When CS is HIGH, the X9401 is deselected and the SO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. CS LOW enables the X9401, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Hold (HOLD) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times.
Device Address (A0 - A1) The address inputs are used to set the least significant 2 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9401. A maximum of 4 devices may occupy the SPI serial bus. Potentiometer Pins VH (VH0 - VH3), VL (VL0 - VL3), RH (RH0 - RH3), RL (RL0 - RL3) The VH/RH and VL/RL inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. VW (VW0 - VW3), RW (RW0 - RW3) The wiper outputs are equivalent to the wiper output of a mechanical potentiometer. Hardware Write Protect Input (WP) The WP pin when LOW prevents nonvolatile writes to the Wiper Counter Registers.
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PIN CONFIGURATION
SOIC VCC VL0/RL0 VH0/RH0 VW0/RW0 CS WP SI A1 VL1/RL1 VH1/RH1 VW1/RW1 V
SS
Array Description
NC VL3/RL3 VH3/RH3 VW3/RW3 A0 SO HOLD SCK VL2/RL2 VH2/RH2 VW2/RW2 NC
1 2 3 4 5 6 7 8 9 10 11 12 X9401
24 23 22 21 20 19 18 17 16 15 14 13
The X9401 is comprised of four resistor arrays. Each array contains 63 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (VH/RH and VL/RL inputs). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (VW/RW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by a Wiper Counter Register (WCR). The six bits of the WCR are decoded to select, and enable, one of sixty-four switches. Wiper Counter Register (WCR) The X9401 contains four Wiper Counter Registers, one for each XDCP potentiometer. The WCR is equivalent to a serial-in, parallel-out register/counter with its outputs decoded to select one of sixty-four switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the Write Wiper Counter Register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers via the XFR Data Register or Global XFR Data Register instructions (parallel load); it can be modified one step at a time by the Increment/Decrement instruction. Finally, it is loaded with the contents of its data register zero (R0) upon power-up. The Wiper Counter Register is a volatile register; that is, its contents are lost when the X9401 is powereddown. Although the register is automatically loaded with the value in R0 upon power-up, this may be different from the value present at power-down. The wiper position must be stored in R0 to insure restoring the wiper position after power-up. Data Registers Each potentiometer has four 6-bit nonvolatile data registers. These can be read or written directly by the host. Data can also be transferred between any of the four data registers and the associated Wiper Counter Register. All operations changing data in one of the data registers is a nonvolatile operation and will take a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, the data registers can be used as memory locations for system parameters or user preference data.
PIN NAMES Symbol
SCK SI, SO A0 - A1 VH0/RH0 - VH3/RH3, VL0/RL0 - VL3/RL3 VW0/RW0 - VW1/RW1 WP VCC VSS NC
Description
Serial Clock Serial Data Device Address Potentiometers (terminal equivalent) Potentiometers (wiper equivalent) Hardware Write Protection System Supply Voltage System Ground No Connection
DEVICE DESCRIPTION The X9401 is a highly integrated microcircuit incorporating four resistor arrays and their associated registers and counters and the serial interface logic providing direct communication between the host and the XDCP potentiometers. Serial Interface The X9401 supports the SPI interface hardware conventions. The device is accessed via the SI input with data clocked in on the rising SCK. CS must be LOW and the HOLD and WP pins must be HIGH during the entire operation. The SO and SI pins can be connected together, since they have three state outputs. This can help to reduce system pin count.
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Data Register Detail
(MSB) D5 NV D4 NV D3 NV D2 NV D1 NV (LSB) D0 NV
I3 I2 I1 I0
Figure 2. Instruction Byte Format
Register Select
R1
R0
P1
P0
Write in Process The contents of the Data Registers are saved to nonvolatile memory when the CS pin goes from LOW to HIGH after a complete write sequence is received by the device. The progress of this internal write operation can be monitored by a Write In Process bit (WIP). The WIP bit is read with a Read Status command. INSTRUCTIONS Identification (ID) Byte The first byte sent to the X9401 from the host, following a CS going HIGH to LOW, is called the Identification byte. The most significant four bits of the slave address are a device type identifier, for the X9401 this is fixed as 0101[B] (refer to Figure 1). The two least significant bits in the ID byte select one of four devices on the bus. The physical device address is defined by the state of the A0 - A1 input pins. The X9401 compares the serial data stream with the address input state; a successful compare of both address bits is required for the X9401 to successfully continue the command sequence. The A0 - A1 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. The remaining two bits in the slave byte must be set to 0. Figure 1. Identification Byte Format
Device Type Identifier Instructions Pot Select
The four high order bits of the instruction byte specify the operation. The next two bits (R1 and R0) select one of the four registers that is to be acted upon when a register oriented instruction is issued. The last two bits (P1 and P0) selects which one of the four potentiometers is to be affected by the instruction. Four of the ten instructions are two bytes in length and end with the transmission of the instruction byte. These instructions are: - XFR Data Register to Wiper Counter Register--This transfers the contents of one specified Data Register to the associated Wiper Counter Register. - XFR Wiper Counter Register to Data Register--This transfers the contents of the specified Wiper Counter Register to the specified associated Data Register. - Global XFR Data Register to Wiper Counter Register --This transfers the contents of all specified Data Registers to the associated Wiper Counter Registers. - Global XFR Wiper Counter Register to Data Register--This transfers the contents of all Wiper Counter Registers to the specified associated Data Registers. The basic sequence of the two byte instructions is illustrated in Figure 3. These two-byte instructions exchange data between the WCR and one of the data registers. A transfer from a data register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action will be delayed by tWRL. A transfer from the WCR (current wiper position), to a data register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the four potentiometers and one of its associated registers; or it may occur globally, where the transfer occurs between all potentiometers and one associated register. Five instructions require a three-byte sequence to complete. These instructions transfer data between the host and the X9401; either between the host and
0
1
0
1
0
0
A1
A0
Device Address
Instruction Byte The next byte sent to the X9401 contains the instruction and register pointer information. The four most significant bits are the instruction. The next four bits point to one of the four pots and, when applicable, they point to one of four associated registers. The format is shown below in Figure 2.
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X9401
one of the data registers or directly between the host and the Wiper Counter Register. These instructions are: - Read Wiper Counter Register-- read the current wiper position of the selected pot, - Write Wiper Counter Register--change current wiper position of the selected pot, - Read Data Register--read the contents of the selected data register; - Write Data Register--write a new value to the selected data register. - Read Status--This command returns the contents of the WIP bit which indicates if the internal write cycle is in progress. The sequence of these operations is shown in Figure 4 and Figure 5. The final command is Increment/Decrement. It is different from the other commands, because it's length is indeterminate. Once the command is issued, the master can clock the selected wiper up and/or down in one resistor segment steps; thereby, providing a fine tuning capability to the host. For each SCK clock pulse (tHIGH) while SI is HIGH, the selected wiper will move one resistor segment towards the VH/RH terminal. Similarly, for each SCK clock pulse while SI is LOW, the selected wiper will move one resistor segment towards the VL/RL terminal. A detailed illustration of the sequence and timing for this operation are shown in Figure 6 and Figure 7.
Detailed Potentiometer Block Diagram
(One of Four Arrays) Serial Data Path From Interface Circuitry Register 0 8 Register 1 6 Parallel Bus Input Wiper Counter Register (WCR)
Serial Bus Input C o u n t e r D e c o d e
VH/RH
Register 2
Register 3
If WCR = 00[H] then VW/RW = VL/RL If WCR = 3F[H] then VW/RW = VH/RH
UP/DN Modified SCL
INC/DEC Logic UP/DN CLK VL/RL
VW/RW
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Figure 3. Two-Byte Command Sequence
CS SCK
SI 0 1 0 1 0 0 A1 A0 I3 I2 I1 I0 R1 R0 P1 P0
Figure 4. Three-Byte Command Sequence (Write)
CS SCL SI 0 1 0 1 0 0 A1 A0 I3 I2 I1 I0 R1 R0 P1 P0 0 0 D5 D4 D3 D2 D1 D0
Figure 5. Three-Byte Command Sequence (Read)
CS SCL SI 0 S0 0 0 D5 D4 D3 D2 D1 D0 1 0 1 0 0 A1 A0 I3 I2 I1 I0 R1 R0 P1 P0
Don't Care
Figure 6. Increment/Decrement Command Sequence
CS SCK
SI 0 1 0 1 0 0 A1 A0 I3 I2 I1 I0 0 0 P1 P0 I N C 1 I N C 2 I N C n D E C 1 D E C n
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Figure 7. Increment/Decrement Timing Limits
tWRID SCK
SI
VW/RW INC/DEC CMD Issued
Voltage Out
Table 1. Instruction Set Instruction
Read Wiper Counter Register Write Wiper Counter Register Read Data Register Write Data Register XFR Data Register to Wiper Counter Register XFR Wiper Counter Register to Data Register Global XFR Data Register to Wiper Counter Register Global XFR Wiper Counter Register to Data Register Increment/Decrement Wiper Counter Register Read Status (WIP bit)
I3 1
1 1 1 1 1 0 1 0 0
I2 0
0 0 1 1 1 0 0 0 1
Instruction Set Operation I1 I0 R1 R0 P1 P0 010 0 P1 P0 Read the contents of the Wiper Counter Register pointed to by P1 - P0 100 0 P1 P0 Write new value to the Wiper Counter Register pointed to by P1 - P0 1 1 R1 R0 P1 P0 Read the contents of the Data Register pointed to by P1 - P0 and R1 - R0 0 0 R1 R0 P1 P0 Write new value to the Data Register pointed to by P1 - P0 and R1 - R0 0 1 R1 R0 P1 P0 Transfer the contents of the Data Register pointed to by R1 - R0 to the Wiper Counter Register pointed to by P1 - P0 1 0 R1 R0 P1 P0 Transfer the contents of the Wiper Counter Register pointed to by P1 - P0 to the Register pointed to by R1 - R0 0 1 R1 R 0 0 0 Transfer the contents of the Data Registers pointed to by R1 - R0 of all four pots to their respective Wiper Counter Register 0 0 R1 R 0 0 0 Transfer the contents of all Wiper Counter Registers to their respective data Registers pointed to by R1 - R0 of all four pots 100 0 P1 P0 Enable Increment/decrement of the Wiper Counter Register pointed to by P1 - P0 010 0 0 1 Read the status of the internal write cycle, by checking the WIP bit.
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Instruction Format
Notes: (1) (2) (3) (4) "A1 ~ A0": stands for the device addresses sent by the master. WPx refers to wiper position data in the Counter Register "I": stands for the increment operation, SI held HIGH during active SCK phase (high). "D": stands for the decrement operation, SI held LOW during active SCK phase (high).
Read Wiper Counter Register (WCR)
device type identifier device addresses instruction opcode 0 0 1 WCR addresses 0 wiper position (sent by X9401 on SO)
CS Falling Edge 0 1 0 1 0 0 A A 1 10
CS W W W W W W Rising PP 0 0 0 P P P P P P Edge 10 543210
Write Wiper Counter Register (WCR)
device type identifier device addresses instruction opcode 0 1 0 WCR addresses 0 Data Byte (sent by Host on SI)
CS Falling Edge 0 1 0 1 0 0 A A 1 10
CS W W W W W W Rising PP 0 0 0 P P P P P P Edge 10 543210
Read Data Register (DR)
device type identifier device addresses instruction opcode DR and WCR addresses Data Byte (sent by X9401 on SO)
CS Falling Edge 0 1 0 1 0 0 A A 1 0 1 1 R R P 10 101
CS W W W W W W Rising P 0 0 P P P P P P Edge 0 543210
Write Data Register (DR)
device type device identifier addresses instruction opcode DR and WCR addresses R 0 P 1 P 0 Data Byte (sent by host on SI)
CS Falling Edge 0 1 0 1 0 0 A A 1 1 0 0 R 10 1
CS W W W W W W Rising 0 0 P P P P P P Edge 543210
HIGH-VOLTAGE WRITE CYCLE
Transfer Data Register (DR) to Wiper Counter Register (WCR)
device type device instruction DR and WCR CS CS identifier addresses opcode addresses Falling Rising Edge 0 1 0 1 0 0 A A 1 1 0 1 R R P P Edge 10 1010
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Transfer Wiper Counter Register (WCR) to Data Register (DR)
device type device instruction DR and WCR CS CS identifier addresses opcode addresses Falling Rising Edge 0 1 0 1 0 0 A A 1 1 1 0 R R P P Edge 10 1010 HIGH-VOLTAGE WRITE CYCLE
Increment/Decrement Wiper Counter Register (WCR)
device type device instruction WCR increment/decrement CS CS identifier addresses opcode addresses (sent by master on SDA) Falling Rising Edge 0 1 0 1 0 0 A A 0 0 1 0 X X P P I/ I/ . . . . I/ I/ Edge 10 10DD DD
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
device type device instruction DR CS CS identifier addresses opcode addresses Falling Rising Edge 0 1 0 1 0 0 A A 0 0 0 1 R R 0 0 Edge 10 10
Global Transfer Wiper Counter Register (WCR) to Data Register (DR)
device type device instruction DR CS CS identifier addresses opcode addresses Falling Rising Edge 0 1 0 1 0 0 A A 1 0 0 0 R R 0 0 Edge 10 10 HIGH-VOLTAGE WRITE CYCLE
Read Status
device type identifier device addresses instruction opcode wiper addresses Data Byte (sent by X9401 on SO)
CS CS Falling W Rising Edge 0 1 0 1 0 0 A A 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 I Edge 10 P
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ABSOLUTE MAXIMUM RATINGS Temperature under bias .................... -65C to +135C Storage temperature ......................... -65C to +150C Voltage on SCK, SCL or any address input with respect to VSS ......................... -1V to +7V V = |(VH-VL)|...................................................... 5.5V Lead temperature (soldering, 10s) .................. +300C COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS Temp Commercial Industrial Min. 0C -40C Max. +70C +85C Device X9401 X9401-2.7 Supply Voltage (VCC) Limits 5V 10% 2.7V to 5.5V
ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Limits Symbol
RTOTAL IW RW VTERM
Parameter
End to end resistance Power rating Wiper current Wiper resistance Voltage on any VH or VL Pin Noise Resolution Absolute linearity (1) Relative linearity (2) Temperature coefficient of RTOTAL Ratiometric temp. coefficient
Min.
-20 -6
Typ.
Max.
+20 50 +6
Unit
% mW mA V dBV %
Test Condition
+25C, each pot Wiper Current = 3mA VSS = 0V Ref: 1kHz Vw(n)(actual) - Vw(n)(expected) Vw(n + 1) - [Vw(n) + MI]
150 VSS -120 1.6 -1 -0.2 300
500 VCC
+1 +0.2 20 10/10/25 0.1 10
MI(3) MI(3) ppm/C ppm/C pF A
CH/CL/CW IAL
Potentiometer capacitances RH, RL, RW leakage current
See Macro model VIN = VSS to VCC. Device is in stand-by mode.
POWER-UP AND DOWN REQUIREMENTS The are no restrictions on the power-up or power-down conditions of VCC and the voltages applied to the potentiometer pins provided that VCC is always more positive than or equal to VH, VL, and VW, i.e., VCC VH, VL, VW. The VCC power-up spec is always in effect.
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (3) MI = RTOT/63 or (VH - VL)/63, single pot
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D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Limits Symbol
ICC1 ICC2 ISB ILI ILO VIH VIL VOL
Parameter
VCC supply current (active) VCC supply current (nonvolatile write) VCC current (standby) Input leakage current Output leakage current Input HIGH voltage Input LOW voltage Output LOW voltage
Min.
Typ.
Max.
400 1 1 10 10
Unit
A mA A A A V V V
Test Conditions
fSCK = 2MHz, SO = Open, Other Inputs = VSS fSCK = 2MHz, SO = Open, Other Inputs = VSS SCK = SI = VSS, Addr. = VSS, CS = VCC VIN = VSS to VCC VOUT = VSS to VCC
VCC x 0.7 -0.5
VCC + 0.5 VCC x 0.1 0.4
IOL = 3mA
ENDURANCE AND DATA RETENTION Parameter
Minimum endurance Data retention
Min.
100,000 100
Unit
Data changes per bit per register years
CAPACITANCE Symbol
COUT
(4)
Test
Output capacitance (SO) Input capacitance (A0, A1, SI, and SCK)
Max.
8 6
Unit
pF pF
Test Condition
VOUT = 0V VIN = 0V
CIN(4)
POWER-UP TIMING Symbol
tr VCC
(6)
Parameter
VCC Power-up rate Power-up to initiation of read operation Power-up to initiation of write operation
Min.
0.2
Max.
50 1 5
Unit
V/ms ms ms
tPUW(5)
tPUR(5)
A.C. TEST CONDITIONS Input pulse levels
Input rise and fall times Input and output timing level VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5
EQUIVALENT A.C. LOAD CIRCUIT
SPICE Macro Model RTOTAL CL 100pF 10pF RW CW 25pF CL 10pF
5V 1533 SDA Output RH
Notes: (4) This parameter is periodically sampled and not 100% tested (5) tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. (6) This is not a tested or guaranteed parameter and should be used only as a guideline.
RL
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AC TIMING Symbol
fSCK tCYC tWH tWL tLEAD tLAG tSU tH tRI tFI tDIS tV tHO tRO tFO tHOLD tHSU tHH tHZ tLZ TI tCS tWPASU tWPAH SSI/SPI clock frequency SSI/SPI clock cycle rime SSI/SPI clock high rime SSI/SPI clock low time Lead time Lag time SI, SCK, HOLD and CS input setup time SI, SCK, HOLD and CS input hold time SI, SCK, HOLD and CS input rise time SI, SCK, HOLD and CS input fall time SO output disable time SO output valid time SO output hold time SO output rise time SO output fall time HOLD time HOLD setup time HOLD hold time HOLD low to output in high Z HOLD high to output in low Z Noise suppression time constant at SI, SCK, HOLD and CS inputs CS deselect time WP, A0 and A1 setup time WP, A0 and A1 hold time 2 0 0 400 100 100 100 100 20 0 50 50 0 500 200 200 250 250 50 50 2 2 500 100
Parameter
Min.
Max.
2.0
Unit
MHz ns ns ns ns ns ns ns s s ns ns ns ns ns ns ns ns ns ns ns s ns ns
HIGH-VOLTAGE WRITE CYCLE TIMING Symbol
tWR
Parameter
High-voltage write cycle time (store instructions)
Typ.
5
Max.
10
Unit
ms
XDCP TIMING Symbol
tWRPO tWRL tWRID
Parameter
Wiper response time after the third (last) power supply is stable Wiper response time after instruction issued (all load instructions) Wiper response time from an active SCL/SCK edge (increment/decrement instruction)
Min.
Max.
10 10 450
Unit
s s ns
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SYMBOL TABLE
WAVEFORM INPUTS Must be steady May change from Low to High May change from High to Low Don't Care: Changes Allowed N/A OUTPUTS Will be steady Will change from Low to High Will change from High to Low Changing: State Not Known Center Line is High Impedance
TIMING DIAGRAMS Input Timing
tCS CS tLEAD SCK tSU SI MSB tH tWL tCYC tLAG
...
tWH
tFI LSB
tRI
...
SO
High Impedance
Output Timing
CS
SCK tV SO MSB tHO
... ...
LSB
tDIS
SI
ADDR
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Hold Timing
CS tHSU SCK tRO SO tHZ SI tHOLD HOLD tLZ tFO tHH
...
XDCP Timing (for All Load Instructions)
CS
SCK
...
MSB
tWRL LSB
SI
...
VW/RW
SO
High Impedance
XDCP Timing (for Increment/Decrement Instruction)
CS
SCK
...
tWRID
VW/RW
... ...
SI
ADDR
Inc/Dec
Inc/Dec
SO
High Impedance
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Write Protect and Device Address Pins Timing
CS WP A0 A1 tWPASU
(Any Instruction) tWPAH
APPLICATIONS INFORMATION Basic Configurations of Electronic Potentiometers
VR +VR
VW/RW
I Three terminal Potentiometer; Variable voltage divider
Two terminal Variable Resistor; Variable current
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Application Circuits
NONINVERTING AMPLIFIER VOLTAGE REGULATOR
VS
+ - VO VIN 317 R1 R2 R1 Iadj R2 VO (REG)
VO = (1+R2/R1)VS
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
OFFSET VOLTAGE ADJUSTMENT
COMPARATOR WITH HYSTERESIS
R1 VS - +
R2
VS
- +
VO
100k
VO
}
}
TL072 10k 10k +5V 10k
R1
R2
VUL = {R1/(R1+R2)} VO(max) VLL = {R1/(R1+R2)} VO(min)
ATTENUATOR
FILTER
C R1 VS R3 R4 All RS = 10k R1 R2 - + VO VS R R2 + - VO
V O = G VS -1/2 G +1/2
GO = 1 + R2/R1 fc = 1/(2RC)
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Application Circuits (continued)
INVERTING AMPLIFIER
EQUIVALENT L-R CIRCUIT
R1
R2
}
VS
}
- +
C1 VO VS
R2 + -
VO = G VS G = - R2/R1
ZIN
R1 R3
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2
FUNCTION GENERATOR
C
- +
R2
R1 - +
} RA } RB
frequency R1, R2, C amplitude RA, RB
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X9401 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45 H 0.25(0.010) M BM
M24.3 (JEDEC MS-013-AD ISSUE C)
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 2.35 0.10 0.33 0.23 15.20 7.40 MAX 2.65 0.30 0.51 0.32 15.60 7.60 NOTES 9 3 4 5 6 7 8 Rev. 1 4/06
MIN 0.0926 0.0040 0.013 0.0091 0.5985 0.2914
MAX 0.1043 0.0118 0.020 0.0125 0.6141 0.2992
A1 B C D E
A1 0.10(0.004) C
e H h L N
0.05 BSC 0.394 0.010 0.016 24 0 8 0.419 0.029 0.050
1.27 BSC 10.00 0.25 0.40 24 0 10.65 0.75 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
18
FN8190.3 October 12, 2006
X9401 Small Outline Package Family (SO)
A D N (N/2)+1 h X 45
A E E1 PIN #1 I.D. MARK c SEE DETAIL "X"
1 B
(N/2) L1
0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X
SEATING PLANE L 4 4
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150") 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300") (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX 0.003 0.002 0.003 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. L 2/01
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 19
FN8190.3 October 12, 2006

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